Generally, when manufacturing a semiconductor, the most used metal materials are aluminum and aluminum alloys. This is because aluminum and aluminum alloys have superior conductivity and a superior adhesive force with an oxide layer, and they can be easily molded.
However, aluminum and aluminum alloys have problems such as electric material migration, hillocks, and spikes.
In detail, if a current is applied to aluminum for a metal interconnection, the diffusion of aluminum atoms may occur in a high-current density area such as an area in contact with silicon or a step area. The diffusion causes a metal line of aluminum existing in the high-current density area to narrow such that a short occurs, which is called “an electric material migration”. Such an electric material migration occurs after a long elapse of time of operation because the aluminum atoms diffuse slowly.
In order to solve such problems, aluminum-copper alloys made by adding a small amount of copper (Cu) to aluminum (Al) must be employed, a step coverage must be improved, or a wide contact area must be designed.
Another problem occurs during an alloying process. In other words, when a heat treatment process is performed, silicon migrates to an aluminum thin film, and an excessive reaction occurs in a predetermined local area, causing a device to be destructed, which is called “a spike phenomenon”.
The spike problem may be solved by employing aluminum-silicon alloys, in which silicon is added by more than a predetermined solubility or by inserting a metal thin film such as TiW or PtSi between aluminum and silicon so as to form a diffusion barrier.
Accordingly, the development of alternative materials for the metal interconnection has been required. Copper (Cu), gold (Au), silver (Ag), cobalt (Co), chromium (Cr), and nickel (Ni) having superior conductivity exists as the alternative materials. Copper and copper alloys, which have low resistivity, superior reliability for electro migration (EM) and stress migration (SM), and economical manufacturing costs, have been widely used.
Accordingly, copper is deposited in a via hole (or a contact hole) and a trench having a single damascene structure or a dual damascene structure so that a plug and a metal interconnection are simultaneously formed, and then undesirable copper remaining on the surface of a wafer is removed through a chemical mechanical polishing (CMP) process.
Hereinafter, a method for forming a conventional metal interconnection of a semiconductor device will be described with reference to accompanying drawings.
FIGS. 1A to 1E are sectional views showing the method for forming the conventional metal interconnection of the semiconductor device.
Referring to FIG. 1A, a first copper thin film is formed on the semiconductor substrate 11 and is selectively removed through a photolithography process, thereby forming a first copper interconnection 12.
Thereafter, a nitride layer 13 is formed on the entire surface of the semiconductor substrate 11 including the first copper interconnection 12, and an interlayer dielectric layer 14 is formed on the nitride layer 13.
The nitride layer 13 is used as an etching stop layer, and the interlayer dielectric layer 14 includes a low K material.
Then, after coating a first photoresist 15 on the interlayer dielectric layer 14, the first photoresist 15 is patterned through an exposure and development process, thereby defining a contact area.
Then, the interlayer dielectric layer 14 is selectively removed by using the first photoresist 15 as a mask and the nitride layer 13 as an etching end point, thereby forming a via hole 16.
Referring to FIG. 1B, the first photoresist 15 is removed, a second photoresist 17 is coated on the entire surface of the semiconductor substrate 11 including the via hole 16, and the second photoresist 17 is patterned through an exposure and development process.
Subsequently, the interlayer dielectric layer 14 is selectively removed from the surface of the resultant structure by a predetermined thickness using the second photoresist 17 as a mask, thereby forming a trench 18.
Referring to FIG. 1C, the second photoresist 17 is removed, and the nitride layer 13 remaining at the lower part of the via hole 16 is etched off.
Thereafter, a metal diffusion blocking layer 19 is formed on the entire surface of the semiconductor substrate 11 including the trench 18 and the via hole 16 by using conductive materials such as titanium (Ti) or titanium nitride (TiN).
Thereafter, a copper (Cu) seed layer is formed on the metal diffusion blocking layer 19, and then a second copper thin film 20a is formed through an electroplating scheme.
Referring to FIG. 1D, a CMP process is performed with respect to the entire surface of the second copper thin film 20a by employing the upper surface of the interlayer dielectric layer 14 as a polishing stop layer, so that the second copper thin film 20a and the metal diffusion blocking layer 19 are selectively polished. Accordingly, a second copper interconnection 20 is formed in the trench 18 and the vial hole 16.
Referring to FIG. 1E, after performing the CMP process, a silicon nitride (SiN) capping layer and a dielectric material are deposited on the interlayer dielectric layer 14, thereby forming a protection layer 22.
However, the method for the conventional metal interconnection of a semiconductor device has the following problems.
In detail, if the silicon nitride (SiN) capping layer and the dielectric material are deposited right after the CMP process so as to form the protection layer 22, CMP residues are created between the copper interconnection 20 and the protection layer 22 adjacent to the copper interconnection 20. Therefore, a micro-bridge may be formed in the reliability test of the semiconductor device. Accordingly, semiconductor defects may be caused.
In addition, the second copper interconnection diffuses toward the dielectric material due to a problem related to a bonding force of the nitride silicon capping layer, so characteristics such as electro migration (EM) and stress migration (SM) may be degraded.